A brand new technology of CMOS picture sensors can exploit all of the picture information to understand a scene, perceive the scenario, and intervene by embedding synthetic intelligence (AI) within the sensor. CEA-Leti researchers have reported this design breakthrough when demand for good picture sensors is rising quickly as a consequence of their high-performance imaging capabilities in smartphones, vehicles, and medical units.
The design breakthrough is constructed on a mix of hybrid bonding and high-density by way of silicon through (HD TSV) applied sciences, which facilitates the combination of assorted elements like picture sensor arrays, sign processing circuits and reminiscence components in picture sensors with precision and compactness.
The design breakthrough relies on a three-layer check car that featured two embedded Cu-Cu hybrid-bonding interfaces, face-to-face (F2F) and face-to-back (F2B), and with one wafer containing high-density TSVs. Supply: CEA-Leti
Communication between the completely different tiers in a picture sensor design necessitates superior interconnection expertise. The brand new design introduced by CEA-Leti employs hybrid bonding as a consequence of its very positive pitch within the micron and sub-micron vary. It additionally makes use of HD TSV, which has an analogous density that permits sign transmission by way of the center tiers.
“Using hybrid bonding and HD TSV applied sciences contribute to the discount of wire size, a essential consider enhancing the efficiency of 3D-stacked architectures,” mentioned Renan Bouis, lead creator of the paper titled “Bottom Thinning Course of Improvement for Excessive-Density TSV in a 3-Layer Integration.” He added that stacking a number of dies to create 3D architectures, akin to three-layer imagers, has led to a paradigm shift in sensor design.
The paper presents the important thing technological bricks which might be necessary for manufacturing 3D, multilayer good imagers able to addressing new functions that require embedded AI. “This units the stage to work on demonstrating a totally useful three-layer, good CMOS picture sensor, with edge AI able to addressing high-performance semantic segmentation and object-detection functions,” mentioned Eric Ollier, undertaking supervisor at CEA-Leti and director of IRT Nanoelec’s Good Imager program.
The Grenoble, France-based analysis home CEA-Leti is a serious accomplice of IRT Nanoelec, an R&D institute additionally based mostly in Grenoble, France.
It’s value mentioning that at ECTC 2023, CEA-Leti scientists reported a two-layer check car combining a 10-μm excessive, 1-μm diameter HD TSV and extremely managed hybrid bonding expertise, each assembled in F2B configuration. Now, they’ve shortened the HD TSV to 6-μm top, which led to the event of a two-layer check car exhibiting low dispersion electrical performances and enabling easier manufacturing.
It’s primarily as a consequence of an optimized thinning course of that allowed the substrate thickness to be lowered with favorable uniformity. “This lowered top led to a 40% lower in electrical resistance, in proportion with the size discount,” mentioned Stéphan Borel, lead creator of the paper titled “Low Resistance and Excessive Isolation HD TSV for 3-Layer CMOS Picture Sensors”. “Simultaneous reducing of the facet ratio elevated the step protection of the isolation liner, resulting in a greater voltage stand up to.”
Scientists at CEA-Leti are assured that this good picture sensor expertise will allow quite a lot of new functions.
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