- AI digital and analog instruments optimized for superior node SF2 gate-all-around (GAA), driving enhanced high quality of outcomes and accelerating circuit course of node migration
- Cadence’s best-in-class 3D-IC expertise enabled for all of Samsung Foundry’s multi-die integration choices, accelerating the design and meeting of stacked chiplets
- Cadence’s broad IP portfolio and instruments for next-generation AI designs will allow clients to attain first-pass silicon success and speed up time to market
Cadence Design Methods, Inc. (Nasdaq: CDNS) at the moment introduced a broad collaboration with Samsung Foundry that features expertise developments to speed up design for AI and 3D-IC semiconductors, together with on Samsung Foundry’s most superior gate-all-around (GAA) nodes. The continuing collaboration between Cadence and Samsung considerably advances system and semiconductor growth for the {industry}’s most demanding purposes, together with AI, automotive, aerospace, hyperscale computing and cellular.
By this shut collaboration, Cadence and Samsung have demonstrated the next:
- AI allows decrease leakage energy and growth of SF2 GAA check chips: Cadence, in shut collaboration with Samsung Foundry, has leveraged the Cadence® Cerebrus Clever Chip Explorer and its AI expertise in each DTCO and implementation to reduce leakage energy on their SF2 GAA platform. In comparison with the best-performing baseline circulate, the Cadence.AI outcome achieved a greater than 10% discount in leakage energy. As a part of this ongoing collaboration, a mutual buyer is actively concerned within the growth of a check chip utilizing Cadence.AI for an SF2 design.
- Cadence bottom implementation circulate licensed for Samsung Foundry SF2: Because of in depth collaboration between Cadence and Samsung Foundry, a whole Cadence bottom implementation circulate has been licensed for the SF2 node to speed up the event of superior designs. The complete Cadence RTL-to-GDS circulate, together with the Genus™ Synthesis Resolution, Innovus™ Implementation System, Quantus™ Extraction Resolution, Pegasus™ Verification System, Voltus™ IC Energy Integrity Resolution and Tempus™ Timing Signoff Resolution has been enhanced to assist bottom implementation necessities resembling bottom routing, nano TSV insertion, placement and optimization, signoff parasitic extraction, timing and IR evaluation, and DRC. The Cadence bottom implementation circulate has been validated with a profitable Samsung SF2 check chip, demonstrating the circulate is prepared to be used.
- Cadence has collaborated with Samsung Foundry to allow options for Samsung Foundry’s multi-die choices: The Cadence Integrity™ 3D-IC platform is enabled for all of Samsung’s multi-die integration choices, and its early evaluation and package deal consciousness options at the moment are compliant with Samsung’s 3DCODE 2.0 model. As well as, Cadence and Samsung have expanded the multi-die collaboration by enabling differentiating applied sciences like thermal warpage evaluation utilizing the Cadence Celsius Studio and system-level LVS with Cadence Pegasus Verification System. Cadence can be supporting Samsung with a package deal PDK that reduces design time with the Allegro X system. Mixed with the Integrity 3D-IC platform, it optimizes the package deal design circulate.
- AI’s Virtuoso Studio circulate efficiently deployed for analog circuit course of migration: Objective-based occasion mapping within the AI-powered Virtuoso Studio supplied speedy retargeting of the schematics, whereas circuit optimization in Virtuoso Studio’s Superior Optimization Platform helped Samsung obtain a 10X enchancment in turnaround time when migrating a 100MHz oscillator design from 14nm to 8nm. As well as, a FinFET-to-GAA analog design migration reference circulate is obtainable for joint clients, with profitable experimental outcomes.
- Cadence mmWave RFIC design circulate efficiently used to tapeout 14RF circuit design: Cadence and Samsung efficiently taped out a 48GHz energy amplifier design, representing silicon validation of the strong, full system reference circulate that leverages the Cadence EMX Designer to create passive units with quick modeling and structure automation. Full design EM extraction with the EMX 3D Planar Solver and EM/IR evaluation utilizing Voltus XFi and Quantus ensured that the IC met aggressive metrics, Pegasus was used for signoff DRC/LVS, whereas AWR VSS supplied a seamless surroundings to hold out preliminary system-level budgeting and post-layout verification. Mutual clients can really feel assured using this circulate to ship modern designs to market in a well timed method.
- Cadence Pegasus Verification System is licensed for Samsung Foundry’s 4nm and 3nm course of applied sciences: By the collaboration with Samsung Foundry, the Cadence bodily verification circulate is optimized to permit mutual clients utilizing Samsung Foundry’s superior nodes to succeed in signoff accuracy and runtime targets for a sooner time to market. The Pegasus system is now licensed throughout a number of superior nodes at Samsung Foundry, that are confirmed and in manufacturing by clients, with simplified, all-inclusive licensing assist. The Pegasus system is built-in into the AI-powered Cadence Virtuoso Studio as iPegasus to allow in-design signoff high quality DRC and interactive metallic fill within the structure implementation, providing as much as 4X sooner turnaround occasions.
- Cadence IP portfolio affords complete {industry} options on superior Samsung nodes:
Cadence’s newest IP constructed on Samsung SF5A consists of industry-leading PHY IP for 112G-ULR SerDes, PCIe® 6.0/5.0, UCIe™ , DDR5-8400, DDR5/4-6400 Reminiscence and USB 2.0, providing clients full platform options.
Cadence’s PHY IP for PCIe 6.0 on Samsung SF5A has been efficiently licensed for PCIe 5.0 x8 compliance and demonstrated seamless interoperability with different PCIe 5.0/6.0 system and check tools, additional showcasing its PCIe resolution maturity
Cadence is furthering its partnership with Samsung Foundry by pushing the efficiency envelope, designing superior reminiscence IP for GDDR7 on Samsung SF4X and SF2, and serving to reshape the HPC/AI {industry} with this new reminiscence normal.
- Superior verification for AI design complexity: Samsung Foundry utilized Cadence’s superior verification applied sciences, such because the Palladium Enterprise Emulation System, JasperC, STG, and Xcelium ML, to sort out rising AI chip complexity and obtain time-to-market necessities in SF3.
“We’re honored to associate with Samsung, a real instance of a chips-to-systems firm, to convey this expertise for our joint companions to design the following technology of clever techniques,” stated Tom Beckley, senior vp and normal supervisor within the Customized IC & PCB Group at Cadence. “The hyperconvergence of AI with fashionable accelerated compute requires a powerful silicon infrastructure. With these new AI-powered, licensed design flows and standardized options, mutual clients can confidently design for Samsung superior nodes whereas reaching their design and time-to-market targets.”
“Samsung and Cadence have an in depth collaboration to advance expertise and assist our clients ship aggressive designs to the market effectively,” stated Sangyun Kim, Vice President and head of Foundry Design Expertise Staff at Samsung Electronics. “Our joint efforts allow clients to make the most of Samsung’s newest course of and expertise improvements to push the bounds for probably the most superior AI, hyperscale computing and cellular SoC designs.”
To be taught extra about Cadence AI choices, please go to: Cadence.ai.