Parsing PWM (DAC) efficiency: Half 3—PWM Analog Filters

Editor’s Observe: This can be a four-part sequence of DIs proposing enhancements within the efficiency of a “conventional” PWM—one whose output is an obligation cycle-variable rectangular pulse which requires filtering by a low-pass analog filter to supply a DAC. The primary half suggests mitigations and eliminations of frequent PWM error sorts. The second discloses circuits pushed from varied V_provide voltages to energy rail-rail op amps and allow their output swings to incorporate floor and V_provide. This third half pursues the optimization of post-PWM analog filters.

 Half 1 may be discovered right here.

 Half 2 may be discovered right here.

Lately, there was a spate of design concepts (DIs) revealed (see Associated Content material) which offers with microprocessor-generated pulse width modulators driving low-pass filters to supply DACs. Approaches have been launched which deal with ripple attenuation, settling time minimization, limitations in accuracy, and allow outputs to achieve and embody floor and provide rails. That is the third in a sequence of DIs proposing enhancements in total PWM-based DAC efficiency. Every of the sequence’ suggestions are implementable independently of the others. This DI addresses low move analog filters.

Wow the engineering world together with your distinctive design: Design Concepts Submission Information

The PWM output

Spectrally, the PWM output consists of a fascinating DC (common) portion and the rest—undesirable AC indicators. With a interval of T, these indicators include power at frequencies n/T, the place n = 1, 2, 3, and many others., that’s, harmonics of 1/T. If the PWM switches between 0 and 1, for each harmonic n there exists an obligation cycle comparable to a peak sign stage of (2/π)/n. This reveals the futility of an attenuation scheme which focuses on a notch or band reject kind of filter—there’ll at all times be a major quantity of power that isn’t attenuated by such. The very best amplitude harmonic is the primary, n = 1. On the very least, this harmonic should be attenuated to a suitable stage, α. Any low move filter that accomplishes it will apply much more attenuation to the remaining harmonics that are already decrease in stage than the primary. In abstract, the seek for the very best filter will deal with what are known as all-pole low move filters, which is one other method of claiming low move filters which lack notch and band-reject options.

The thin on low move all-pole filters

Analog filters may be outlined as a ratio of two polynomials within the advanced (actual plus imaginary) variable s:

The place I ≤ Ok. The phrases z_i and p_i are referred to respectively because the zeroes and the poles of the filter. Ok is the order (first, second, and many others.) of the filter in addition to the variety of its poles. All-pole filters of unity achieve at DC may be specified merely as:

Filter sorts embody Butterworth, Bessel, Chebyshev, and others. These make totally different trade-offs between the aggressiveness of attenuation with rising stop-band frequency and the rapidity of settling in response to a time area impulse, step, or different disturbance. Enhancing certainly one of these typically denigrates the opposite. Tables of poles for varied orders and sorts of these filters may be discovered within the reference [1]. Values given are for filters which at roughly 1 radian per second (2π Hz) exhibit 3 dB of attenuation with respect to the extent at DC. This level is taken into account to be the transition between the low frequency move and excessive frequency cease bands. Multiplying all poles by a frequency scaling issue (FSF) will trigger the filter to attenuate 3 dB at 2π·FSF Hz. The frequency response of a filter may be calculated by substituting j·2π·f for s in H(s) and taking the magnitude of the sum of the true and imaginary elements. Right here, j = √-1 and f is the frequency in Hz.

The time area response of a filter to a change in PWM obligation cycle reveals how rapidly it can settle to the brand new obligation cycle common. For a filter of unity achieve at DC, this entails subtracting from 1 the inverse Laplace rework of H(s)/s. A dialogue of Laplace transforms, their inverses, and sensible makes use of is past the scope of this DI. These inverse transforms can, nevertheless, be readily decided through the use of a web-based instrument [2].

Necessities of an optimum filter

A filter should attenuate the utmost worth over all obligation cycles (2/π) of the PWM first harmonic by an element of α. A b-bit PWM has a decision of Full-Scale·2^-b. So, for the primary harmonic peak to be no higher than ½ LSB, α needs to be set to (π/2)·2^-(b+1). Asking for extra attenuation would gradual the filter response to a step change in obligation cycle. From the time area perspective, the time t_s needs to be minimized for the filter to settle to +/- α · Full Scale in response to an obligation cycle change from Full Scale to zero.

In direction of an optimum filter

Think about a 12-bit PWM clocked from a 20 MHz supply. The frequency of its first harmonic is F₀ = 4883 Hz, and its α is 1.917·10^-4. 3^rd, 5^th, and seven^th order filters of sorts Bessel, Linear Part .05° and .5° Equiripple error, Gaussian 6 dB and 12 dB, Butterworth, and .01 dB Chebyshev are thought-about. These are roughly so as of more and more aggressive attenuation with frequency coupled with rising settling occasions. Acceptable FSFs are wanted to multiply the poles (listed in reference [1]) of every filter to attain attenuation α at F₀ Hz. Excel’s Solver [3] was used to seek out these components. The scaled values had been divided by 2π to transform them to Hertz and utilized to LTspice’s [4] 2ndOrderLowpass filter objects in its Particular Features folder to assemble full filters. The graph in Determine 1 reveals the frequency responses of 24 scaled filters. These embody 3^rd, 5^th, and seven^th order variations of the filter sorts listed above. These filters had been named after the mathematicians who developed the mathematics describing them (I’ve for some purpose failed to seek out any details about Mr. or Ms. Equiripple). Moreover, there are the identical three orders of yet another filter kind that was developed by the writer and can be described later. Though the writer makes no claims of being a mathematician, for need of another, these have been named Paul filters. (An appalling selection, I’m certain you’ll agree.)

Determine 1 The frequency response of 24 scaled filters together with embody 3^rd, 5^th, and seven^th order variations of the 7 filter sorts listed above (Bessel, Linear Part, Equiripple, Gaussian, Butterworth, Chebyshev and the Paul filter developed by the writer) the place the worth of α is depicted by the horizontal pink line.

In Determine 1, the worth of α is depicted by the horizontal line. It and all of the filter responses intersect at a frequency of F₀ (the PWM’s first harmonic) satisfying the frequency response attenuation requirement. Determine 2 is the Bessel filter portion of the LTspice file which generates the above graph. The irregular pentagons are LTspice’s 2ndOrderLowPass objects. The resistors and capacitors implement first order sections. H = 1 is the filter’s achieve at DC.

Determine 2 The Bessel filter portion of the LTspice file which generates the response in Determine 1, U1-U6 are LTspice’s 2ndOrderLowPass objects, resistors and capacitors implement first order sections, and H = 1 is the filter’s achieve at DC.

By altering the “.ac dec 100 100 10000” command within the file to “.tran 0 .01 0”, changing the “SINE (0 1) AC 1” voltage supply with a pulsed supply “PULSE(1 0 0 1u 1u .0099 .01)” and operating the simulation, the response of those filters to an obligation cycle step from 1 V to 0 V is obtained as proven in Determine 3.

Determine 3 Changing the AC voltage supply with a pulsed supply to vary the obligation cycle step of the filter response from 1 V to 0 V.

Oh, what a stunning mess! The vertical scale is the frequent log of absolutely the worth of the response—absolute worth as a result of the response oscillates round zero, and log due to the big dynamic vary between 1 and α, the latter of which is once more proven as a horizontal line.

Which filter’s absolute response settles (reaches and stays lower than α) within the shortest time frame? To seek out the reply to that query, use is manufactured from LTspice’s “Export knowledge as textual content” characteristic below the “File” possibility made out there by right-clicking contained in the plot. This knowledge is then imported into Excel. Every filter’s knowledge is parsed backwards in time ranging from 10 ms. The primary instants when the responses exceed α are recorded. These are the occasions that the filters require to settle to α. (As may be seen, there have been some that require greater than 10 ms to take action.) For every filter order, it was decided which sort had the shortest settling time. Desk 1 reveals the settling occasions to ½ LSB for 8-bit by means of 16-bit PWMs of three^rd, 5^th, and seven^th orders of filters of varied sorts.

Desk 1 Settling occasions to ½ LSB for 8-bit by means of 16-bit PWMs of three^rd, 5^th, and seven^th orders for varied sorts of filters. The quickest settling occasions are proven in daring pink whereas people who did not settle inside 10 ms are gray and listed as “> 10 ms”.

The entries in every desk row with the quickest settling time is proven in daring pink. These which did not settle inside 10 ms are listed as > 10 ms and are greyed-out. On the whole, the 7^th orders settled quicker than the 5^th orders, which had been noticeably quicker than the three^rd’s. Additionally, these with the decrease Q sections settled quicker than the upper Q options (once more, see the tables in reference [1]). The Chebyshev filters with ripples higher than .01 dB (not depicted) for example, had increased Q’s than all those listed above and had hopelessly lengthy settling occasions.

As a bunch, the Paul filters settled the quickest, however that doesn’t preclude the number of one other filter in an occasion when it settles quicker. Nonetheless, it’s price discussing how the Pauls had been developed. Beginning with the three^rd, 5^th, and seven^th order frequency-scaled Bessel poles, the Excel Solver evaluated the inverse Laplace transforms of the filters’ capabilities H(s). It was instructed to differ the pole values whereas minimizing the utmost worth of the filter response after a given time t_s. This was made topic to the constraint that the amplitude response of |H(2πj·F₀)| be α, the place F₀ = 20MHz / 2¹² and α = (π/2)·2^-(12+1). If the utmost response exceeded α for a given t_s, t_s was elevated. In any other case t_s was decreased. A number of runs of Solver led to the ultimate set of filter poles. It’s attention-grabbing that regardless that the optimization was run for a 12-bit PWM solely, settling occasions at different bit lengths between 8 and 16 continues to be fairly good and normally superior to these of the opposite well-known filters. The Paul filter poles and Qs are listed in Desk 2.

Desk 2 The poles and Qs for 3^rd, 5^th, and seven^th order Paul filter.

Desk 3 contains FSFs for the poles of the well-known filters. The unscaled poles are given within the tables of reference [1]. The scaled poles are attribute of filters which additionally attenuate a frequency of F₀ by an element of α.

Desk 3 The FSFs for the poles of the well-known filters within the tables of reference [1] for the values of α and F₀.

 Implementing a filter

A place to begin for the implementation of a filter whose poles are taken from a reference desk is to use to these poles an acceptable FSF.  These components are given for well-known filters in Desk 3 for an attenuation, α, at a frequency of F₀ Hz. In Desk 2, the Paul filter poles have already been scaled as such. For any of those filters, to vary the α from a frequency F₀ to F₁ Hz, the poles needs to be multiplied by an FSF of F₁/F₀.

In settling rapidly to the small worth of α, a few of the greatest errors in filter efficiency are attributable to element tolerances. To restrict these errors, resistors needs to be metallic movie, 1% at worst with 0.1% most well-liked.  Capacitors needs to be NPO or C0G for temperature and DC voltage stability, 2% at worst and 1% most well-liked. Smaller worth resistors end in a quieter design and result in smaller offset voltages attributable to op amp enter bias and offset currents. Nonetheless, these additionally require larger-valued, greater, and costlier capacitors. Hold these restrictions in thoughts when continuing with the next steps.

For a primary order part with pole ω:

1. Begin by guessing values of R and C such that RC = 1/ω.
2. Select a typical worth NPO or COG capacitor near that worth of C.
3. Calculate R’ = 1/(ω·C) the place C is that commonplace worth capacitor.
4. Select for R the subsequent smaller commonplace worth of R’ and make up the distinction with one other smaller resistor in sequence. Though this won’t compensate for the elements’ 1% and a pair of% tolerances, it can yield a end result which is perfect on common.
5. Join one terminal of R to the PWM output and the opposite to the capacitor C (floor its different facet) and to the enter of a unity achieve op amp. If achieve is required within the combination filter, it’s this op amp which ought to provide it fairly than one which implements a second order part; in contrast to second order sections, achieve on this op amp has no impact on the R-C part’s AC traits as a result of there is no such thing as a suggestions to the passive elements. The output of this op amp ought to drive the cascade of remaining second order sections (Determine 4).

Determine 4 Really useful configuration the place one terminal of R is linked to the PWM output, and the opposite is linked to the capacitor C (floor its different facet) and to the enter of a unity achieve op amp.

For second order sections with pole ω and high quality issue Q, error sources are once more element values. Errors may be exacerbated by the selection of a filter topology. A second order Sallen Key [5] part with the least sensitivity employs an op amp configured for unity achieve as proven in Determine 5.

Determine 5 A second order Sallen Key part with the least sensitivity employs an op amp configured for unity achieve.

To pick element values:

1. Begin by selecting values of R and C such that RC = 1/ω.
2. Select commonplace values of C₁ and C₂ much like C such that C₁ / C₂ is as massive as potential, however no bigger than 4Q². Making a desk of all potential capacitor ratios is useful in choosing the optimum ratio.
3. Calculate D = (1 – 4Q²·C₂/C₁)^0.5 and W = 2·Q·C₂·ω
4. For R_1a, choose a typical resistor worth barely lower than (1 + D)/W and add R_1b in sequence to make up the distinction.
5. For R_2a, choose a typical resistor worth barely lower than (1 – D)/W and add R_2b in sequence to make up the distinction.
6. If there are multiple second order part, the sections needs to be linked so as of reducing values of Q to attenuate noise.

A PWM filter instance

Think about a 5^th order Paul filter with an attenuation of α at a frequency F₁ = F₀/2. Every of the ω values within the Paul filter desk could be multiplied by an FSF of F₁/F₀ = ½, however the Q’s could be unchanged. The next schematic proven in Determine 6 satisfies these constraints.

Determine 6 A 5^th order Paul filter scaled to function at F₀/2 Hertz.

 Designing PWM analog filters

A set of tables itemizing settling occasions to inside ½ LSB of 8 by means of 16-bit PWMs of interval 204.8 µs (1/4883 = 1/F₀ Hz) has been generated for 3^rd, 5^th, and seven^th order variations of eight totally different filter sorts. These filters attenuate the height worth of regular state PWM-induced ripple to ½ LSB. From these listings, the filter with the quickest settling time is instantly chosen. These filters may be tailored to a brand new PWM interval by multiplying their poles by a scaling issue equal the ratio of the outdated to new intervals. New settling occasions are obtained by dividing those within the tables by that very same ratio.

Pole scaling components for the operation of well-known filters at F₀ are provided in a separate desk. The poles of those filters can be found in reference [1] and needs to be multiplied by the related issue to perform this. A brand new “Paul” filter (already scaled for F₀ operation) has been developed which normally has quicker settling occasions than the well-known ones whereas offering the mandatory PWM ripple attenuation. As with the others, it too may be scaled for operation at totally different frequencies.

It needs to be famous that element tolerances will result in filters with attenuations and settling occasions which differ considerably from the calculations offered. Nonetheless, it is sensible to make use of filters with the smallest calculated settling time values.

Christopher Paul has labored in varied engineering positions within the communications trade for over 40 years.

Associated Content material

• Double up on and ease the filtering necessities for PWMs
• Optimizing a easy analog filter for any PWM
• Quick-settling synchronous-PWM-DAC filter has nearly no ripple
• Cancel PWM DAC ripple and energy provide noise
• Cancel PWM DAC ripple with analog subtraction
• Cancel PWM DAC ripple with analog subtraction—revisited
• Cancel PWM DAC ripple with analog subtraction however no inverter
• Quick PWM DAC has no ripple

 References

1. http://www.analog.com/media/en/training-seminars/design-handbooks/basic-linear-design/chapter8.pdfpercent20 (particularly Figures 8.26 by means of 8.36. This reference does an excellent job of describing the variations between the filter response sorts and filter realization on the whole.)
2. https://www.wolframalpha.com/enter?i=inverse+Laplace+rework+p*bpercent5E2percent2Fpercent28percent28spercent5E2percent2Bbpercent5E2percent29*%28spercent2Bppercent29percent29
3. https://help.microsoft.com/en-us/workplace/define-and-solve-a-problem-by-using-solver-5d1a388f-079d-43ac-a7eb-f63e45925040
4. https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html
5. https://www.ti.com/lit/an/sloa024b/sloa024b.pdf

The submit Parsing PWM (DAC) efficiency: Half 3—PWM Analog Filters appeared first on EDN.