Three Papers Report:
- stacking an AlGaN/GaN/Si HEMT on CPW traces fabricated on 200mm substrate,
- stacking 5G-compatible (30GHz) RF circuits instantly above a working digital circuit, and
- unlocking a low-temperature showstopper in 400°C analog gadgets.
CEA-Leti scientists introduced three papers on the IEEE Symposium on VLSI Expertise and Circuits detailing the institute’s progress on 3D integration applied sciences, that are a promising strategy for designing Extra than Moore techniques, particularly radio frequency (RF) built-in techniques.
3D integration methods allow high-density CMOS transistors to coexist with transistors manufactured from III-V supplies, which may attain energy ranges and frequencies unattainable with standard silicon applied sciences. Potential functions embrace communications, the web of issues, medical gadgets and automotive sensing.
‘RF Performances Are Aggressive with Different 3D Options’
The paper, “Hybrid Integration of 3D-RF Interconnects on AlGaN/GaN/Si HEMT RF Transistor that includes 2.2W/mm Psat & 41% PAE @28GHz utilizing a Strong and Price-Efficient Chiplet Heterogeneous Bonding Approach”, stories the stacking of an AlGaN/GaN/Si excessive electron mobility transistor (HEMT) on coplanar-waveguide (CPW) traces fabricated on 200mm silicon trap-rich substrate. The HEMT and CPWs traces have been interconnected with copper pillars (CuPi) utilizing a high-yield chiplet heterogeneous integration course of.
“Because of the integration of low insertion loss CuPi interconnects – 0.1dB@28GHz and a cautious administration of the warmth dissipation inside the 3D construction – the HEMT transistor options an output energy density of two.2W/mm @10V & a peak PAE of 41 %,” the paper stories.
“These RF performances are aggressive with different 3D options discovered within the literature,” mentioned Alexis Divay, lead creator of the paper. “Our industrial-grade 3D meeting strategy is very promising for fabricating environment friendly and cost-effective 3D-RF III-V techniques.”
‘Outcomes Lay the Groundwork for Utilizing 3D Applied sciences to Allow RF Purposes’
The paper, “First Radio-Frequency Circuits fabricated in top-tier of a full 3D Sequential Integration Course of at mmW for 5G functions”, particulars how for the primary time 5G-compatible (30GHz) RF circuits have been stacked instantly above a working digital circuit. The analog silicon RF circuits, sequentially fabricated at 500°C above a digital circuit layer with a 28nm FD-SOI industrial platform, introduced efficiency in keeping with commonplace, thermal-budget FD-SOI gadgets.
“Each top- and bottom-tier circuits are absolutely practical with good efficiency after the 3D-SI course of,” mentioned lead authors José Lugo and Jean-Baptiste David. “Furthermore, we explored a worst-case state of affairs to evaluate potential detrimental impacts of the ultra-thin proximity between analog-RF circuits and the digital layer. The work demonstrated the feasibility of vertical co-integration with none degradation, regardless of the shut neighborhood of each tiers. These outcomes lay the groundwork for utilizing 3D applied sciences to allow to RF functions.”
‘CEA-Leti Creates a Path Towards a Second Step in 3D Silicon-Integration Growth’
The paper, “Breakthrough processes for Si CMOS gadgets with BEOL compatibility for 3D sequential built-in Extra than Moore analog functions”, stories unlocking low-temperature “showstoppers” in versatile analog high-voltage (>2.5V) BEOL (400°C) gadgets.
“We demonstrated for the primary time the nanosecond laser annealing, solid-phase epitaxial regrowth on a whole system, which surpasses the low-temperature, dopant activation technological showstopper,” mentioned Daphnée Bosch, lead creator of the paper.
The paper notes that the work additionally “demonstrated monocrystalline silicon gadgets with a CMOS-compatible poly gate due to nanosecond laser annealing in soften regime and junction dopants activation with out diffusion at 400°C.” This preserves the engineered junction profile. “HPD2 last anneal cures low-temperature gate stack, reaching performances in keeping with planar analog CMOS expertise.”
Co-author Perrine Batude mentioned a few of CEA-Leti’s industrial companions have already got launched part of its imaginative and prescient: a second system layer built-in sequentially utilizing monocrystalline channel bonding above a backside system. Nevertheless, the highest pixel MOSFETs are at present processed at 1,000°C.
“With this paper, CEA-Leti creates a path towards a second step in 3D-silicon integration improvement with 400°C high gadgets stackable above a much less resilient backside tier,” she mentioned.
Fourth Paper
A fourth paper introduced by the institute on the convention lined “A Present-Supply-Free Fixed-Present Wi-fi Adiabatic Neural Stimulator Reaching a 5.5-27.7x Improved RF-to-Electrode Stimulation Effectivity Issue”.