Ahead-looking: TSMC has scheduled its performance-optimized N3P node to enter mass manufacturing within the second half of 2024, but it surely’s not too quickly to see what else the chipmaker has in retailer for the longer term. N3X, N2, N2P and A16 nodes, are coming in 2025 and 2026, bringing completely different strengths to the market, similar to TSMC’s first use of gate-all-around (GAA) nanosheet transistors in N2. Then there’s A16, launched solely final month, that will likely be very best for HPC merchandise with advanced sign routes and dense energy supply networks.
The competitors to provide the world’s most superior chips is fierce, and TSMC’s product roadmap guarantees that the battle for supremacy will likely be intense. First, its performance-optimized N3P node is coming, set to enter mass manufacturing within the second half of 2024 and would be the firm’s most superior node for some time.
Subsequent 12 months, nonetheless, TSMC will introduce two manufacturing nodes that may enter high-volume manufacturing within the second half of 2025, promising to speed up some great benefits of N3P. These nodes are N3X, a 3nm-class course of, and N2, a 2nm-class course of.
N3X is tailor-made for high-performance computing functions, with a most voltage of 1.2V. In accordance with analysis compiled by AnandTech, N3X chips can both scale back energy consumption by 7% by reducing Vdd from 1.0V to 0.9V, improve efficiency by 5%, or improve transistor density by round 10%.
N2 makes use of gate-all-around (GAA) nanosheet transistors – a primary for TSMC – and options distinctive low Vdd efficiency that’s designed for cell and wearable functions. As well as, N2’s ultra-thin stacked nanosheets ship a brand new stage of vitality environment friendly computing for HPC, TSMC says. Bottom energy rail will even be added to spice up efficiency even additional.
N2 know-how will include TSMC NanoFlex, a design-technology co-optimization that gives designers with flexibility in N2 normal cells, with quick cells emphasizing small space and larger energy effectivity, and tall cells maximizing efficiency. Clients are in a position to optimize the mixture of quick and tall cells throughout the identical design block.
In 2026, TSMC will introduce two extra nodes: N2P (2nm-class) and A16 (1.6nm-class).
N2P is anticipated to ship a 5% – 10% decrease energy or a 5% – 10% greater efficiency in comparison with the unique N2. Nonetheless, opposite to prior bulletins, N2P is not going to incorporate a bottom energy supply community, utilizing standard energy supply mechanisms as a substitute. This implies the combination of such superior energy supply will shift to future era nodes, together with A16.
TSMC introduced A16 final month. A16 will mix TSMC’s Tremendous Energy Rail structure with its nanosheet transistors, bettering logic density and efficiency by dedicating front-side routing sources to alerts, making A16 very best for HPC merchandise with advanced sign routes and dense energy supply networks. In comparison with TSMC’s N2P course of, A16 will present 8-10% pace enchancment on the identical Vdd (optimistic energy provide voltage), 15-20% energy discount on the identical pace, and as much as 1.10X chip density enchancment for knowledge middle merchandise.