Cadence Unveils Palladium Z3 and Protium X3 Techniques to Usher in a New Period of Accelerated Verification, Software program Growth and Digital Twins

Cadence Design Techniques, Inc. (Nasdaq: CDNS) at the moment introduced the brand new Cadence^® Palladium^® Z3 Emulation and Protium^™ X3 FPGA Prototyping techniques, a revolutionary digital twin platform that builds on the success of the industry-leading Palladium Z2 and Protium X2 techniques to sort out escalating system and semiconductor design complexity, and to speed up the event timeline for probably the most superior SoCs. Palladium and Protium techniques have lengthy been trusted by market-shaping AI, automotive, hyperscale, networking and cellular chip corporations to ship the best throughput pre-silicon {hardware} debug and pre-silicon software program validation. Focused on the {industry}’s largest multi-billion-gate designs, the brand new Palladium Z3 and Protium X3 techniques set a brand new customary of excellence, offering clients with greater than a 2X improve in capability and a 1.5X efficiency improve in comparison with previous-generation techniques, enabling sooner design bring-up and shortening total time to market.

“As generational drivers speed up the necessity for system and semiconductor innovation, our clients are dealing with rising challenges to energy probably the most superior functions,” mentioned Paul Cunningham, senior vice chairman and basic supervisor of the System Verification Group at Cadence. “The third era Palladium and Protium dynamic duo techniques are core elements of the Cadence Verification Suite and seamlessly interface with the Verisium AI-driven Verification Platform. The Cadence verification full move presents our clients the best verification throughput wanted to ship their {hardware} improvements to market sooner and to assist the speedy improvement of latest applied sciences, comparable to generative AI.”

The Palladium Z3 and Protium X3 techniques supply elevated capability, and scale from job sizes of 16 million gates as much as 48 billion gates, so the most important SoCs could be examined as a complete slightly than simply partial fashions, guaranteeing correct performance and efficiency. The techniques are powered by the NVIDIA BlueField DPU and NVIDIA Quantum InfiniBand networking platforms and keep congruency when transitioning between the 2 techniques and transitioning from digital to bodily interfaces and vice versa. The Palladium Z3 system accelerates {hardware} verification, and thru useful and interface congruency, fashions could be rapidly introduced up onto the Protium X3 system for accelerated software program validation.

“The supercharged Palladium Z3 and Protium X3 are constructed to ship quick pre-silicon verification and validation of the most important and most complicated units,” mentioned Dhiraj Goswami, company vice chairman, {Hardware} System Verification R&D at Cadence. “Our progressive customized silicon and system structure, mixed with revolutionary modular compile and debug capabilities enabling a number of turns per day, continues to push the envelope to satisfy our clients’ wants, permitting them to resolve the world’s hardest challenges and allow their subsequent era of improvements to develop into a actuality.”

“Constructing environment friendly, high-performance AI platforms requires refined infrastructure and integration throughout a full stack of optimized techniques and software program,” mentioned Scot Schultz, senior director, Networking at NVIDIA. “Accelerated by NVIDIA networking, the next-generation Cadence Palladium and Protium techniques push the boundaries of capability and efficiency to assist allow a brand new period of generative AI computing.”

With the Palladium Z3 system’s new domain-specific apps, customers have entry to probably the most full providing for managing rising system and semiconductor design complexity, bettering system-level accuracy, and accelerating low-power verification. The domain-specific apps embrace the {industry}’s first 4-State Emulation App, the Actual Quantity Modeling App, and the Dynamic Energy Evaluation App.

“As SoCs develop into extra complicated, scalable validation and verification instruments that allow large software program testing earlier than tapeout are extra crucial than ever,” mentioned Tran Nguyen, senior director of design providers, Arm. “The newest {hardware} verification platforms and instruments from Cadence are sparking innovation in Arm IP design for AI, automotive, and knowledge heart functions, and we sit up for how it will profit our mutual clients.”

“Delivering on management computing merchandise requires AMD to carry collectively a mess of pre-silicon options and strategies to satisfy the size of the verification problem,” mentioned Alex Starr, Company Fellow, AMD. “Cadence Palladium Z3 and Protium X3 techniques add to our capabilities between emulation and enterprise prototyping to enhance design productiveness and meet time-to-market targets. Our collaboration with Cadence additionally incorporates the AMD Versal™ Premium VP1902 adaptive SoC inside the Protium X3 system in addition to AMD EPYC™ processor-based host servers certified for each the Palladium Z3 and Protium X3 techniques to allow excessive capability with next-level efficiency and scalability.”

The Palladium Z3 and Protium X3 techniques are a part of the broader Cadence Verification Suite and assist the corporate’s Clever System Design^™ technique, enabling SoC design excellence. The techniques have been deployed at choose clients, with basic availability anticipated in Q3 2024. For extra info on the brand new Palladium Z3 and Protium X3 techniques, please go to www.cadence.com/go/dynamicduo3.