A few of the commentary in response to Half 1 on this matter steered that the 2 1 pF capacitors, C4 and C5, needed to be put in collection for lack of availability of 0.5 pF elements.
A simulation of that introduced circuit is seen as follows:
Determine 1 The circuit with a floating node and its Bode plot simulation.
Half alternatives differ considerably from the unique. These op-amps are digital, the JFET is merely an accessible half from the simulation software program and the diode represents the unique photodiode. For all of that, these are all shut sufficient. Please notice the Bode plot of this configuration.
To maintain utilizing the pair of 1 pF capacitors, the next schematic is identical as above however with the addition of yet another resistor, R8, in parallel with C4.
Determine 2 The circuit with out a floating node (a further resistor R8 added in parallel with C4) and its Bode plot simulation.
At 10 MΩ, resistor R8 supplies a DC path for the previously floating node to maintain that node’s voltage from unpredictably shifting. Word that the Bode plot for this modified circuit is indistinguishable from the plot seen earlier than.
Different choices for tethering the previously floating node exist as nicely. For instance, R8 might be tied from the C4 and C5 junction to floor, once more, with no seen impact on the Bode plot.
The only option is greatest left to the designer.
John Dunn is an electronics marketing consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York College (MSEE).
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