Editor’s Word: It is a four-part sequence of DIs proposing enhancements within the efficiency of a “conventional” PWM—one whose output is an obligation cycle-variable rectangular pulse which requires filtering by a low-pass analog filter to provide a DAC. The primary half suggests mitigations and eliminations of widespread PWM error varieties. The second discloses circuits pushed from numerous Vprovide voltages to energy rail-rail op amps and allow their output swings to incorporate floor and Vprovide. The third pursues the optimization of post-PWM analog filters. This fourth half pursues the optimization of post-PWM analog filters.
Half 1 may be discovered right here.
Half 2 may be discovered right here.
Half 3 may be discovered right here.
Not too long ago, there was a spate of design concepts (DIs) printed (see Associated Content material) which offers with microprocessor-generated pulse width modulators driving low-pass filters to provide DACs. Approaches have been launched which handle ripple attenuation, settling time minimization, and limitations in accuracy. That is the fourth in a sequence of DIs proposing enhancements in total PWM-based DAC efficiency. Every of the sequence’ suggestions is implementable independently of the others. This DI addresses PWM sequence modifications which ease low move analog filtering necessities.
Wow the engineering world together with your distinctive design: Design Concepts Submission Information
The tyranny of decision vs response time
The mixture of PWM clock frequency Fclk Hz and the variety of bits b of PWM decision dictates the bottom frequency (Fclk·2-b Hz) output element of a regular PWM. Over all of the doable responsibility cycles, this element can be the most important and subsequently essentially the most difficult for an analog filter to suppress. For a given Fclk, the extra bits of decision, the longer the settling time can be of a filter which offers enough suppression. However there’s a means round this limitation.
Suppose a regular 8-bit PWM whose output is both 0 or 1 is configured for an obligation cycle of (arbitrarily) 121/256. The primary 121 states in a 256-state cycle could be 1 and the remaining 135 could be 0’s. However what if the primary 128 states began with 60 ones and the final 128 states began with 61 ones? Let’s name this the “split-in-two” PWM. These two sequences have been offset in amplitude barely in order that they are often clearly seen on a graph proven in Determine 1.
Determine 1 Output sequences of ordinary and split-in-two 8-bit PWMs with the identical clock frequency, interval, and responsibility cycle (121/256).
The blue waveform represents the usual PWM and the orange one is the split-in-two PWM. Why may the latter be advantageous? Contemplate the spectra of the 2 PWMs seen in Determine 2.
Determine 2 Frequency content material of ordinary and split-in-two 8-bit PWMs with the identical clock frequency, interval, and responsibility cycle (121/256).
The vitality within the first harmonic of the split-in-two PWM is negligible compared with that of the usual PWM. The required attenuation for the primary harmonic has been considerably lessened, and that which was required is now utilized to the harmonic at double the frequency. A much less aggressive attenuation-with-frequency analog filter can now be employed, leading to a shorter settling time in response to a change in responsibility cycle.
One other means to have a look at that is to double the split-in-two PWM interval to 512 states to provide a 9-bit PWM. As proven in Determine 3, the spectra of the 2 PWMs are virtually equivalent as a result of the time area waveforms are virtually equivalent—they differ solely in that each different 256-bit sequence, one extra one-state replaces a zero-state. The upper decision 9-bit PWM produces a small quantity of vitality (lower than 1%) at half the frequency of the 8-bit’s basic. Any analog low move filter with enough suppression of the 8-bit basic frequency will greater than sufficiently attenuate the sign at half that frequency.
Determine 3 Frequency content material of a regular 8-bit PWM of responsibility cycle 121/256 and a split-in-two 9-bit PWM of responsibility cycle (121.5/256). They share the identical clock, however the split-in-two’s interval is twice the usual PWM’s.
The super-cycle
We will consider the split-in-two as producing a “super-cycle” consisting of two cycles of twob states, every having at the least S one-states, with 0 ≤ S < 2b. In a single cycle, one zero-state might be swapped for a one-state if the overall variety of ones within the super-cycle is odd. It is a (b+1)-bit PWM with a interval of twob+1 states. However there isn’t a motive to cease at two. There could be a super-cycle of twon cycles the place n is any integer. With every cycle able to optionally swapping one zero-state for a one-state, this results in a PWM super-cycle with a decision of twob+n bits. However not like commonplace, non-super-cycle PWMs whose most spectral vitality element is at fclk/2b+n Hz, the super-cycle’s is at a a lot increased fclk/2b Hz. As with the precise case of the split-in-two, this eases analog filtering necessities and leads to a shorter settling time.
It’s value considering of a super-cycle as consisting of the sum of two totally different sequences. One is the S-sequence during which each cycle consists of an equivalent sequence of S contiguous one-states. The opposite is the X-sequence the place every cycle optionally swaps the primary zero-state following the final one-state with one other one-state. The X-sequence has X one-states the place 0 ≤ X < 2n. The responsibility cycle of the super-cycle is then (2n·S + X)/2b+n.
When n = 1 for a super-cycle, there is just one cycle the place an additional one-state can reside. However when n > 1, X can be higher than one and the query turns into easy methods to distribute the X ones among the many 2n cycles in order to attenuate the super-cycle’s vitality at low frequencies. The superb people at Microchip who manufacture the SAM D21 microcontroller not solely have figured this out for us, however they’ve additionally carried out it in {hardware} [1]! For this IC, it’s essential solely to write down the values of X and S to separate registers to implement a super-cycle PWM; the {hardware} does the remainder unsupervised. Fortuitously, it’s easy for nearly any microprocessor to reinforce a regular PWM to implement a super-cycle. For every PWM cycle, the responsibility cycle depend should be modified in order that instantly after the sequence of S ones, the primary zero will get modified to a one if and provided that the next C expression is true for that cycle:
MASK & (cycleNbr * X) > MASK – X
Right here, MASK = 2n– 1, X is as earlier than, and cycleNbr is the numeric place of the cycle within the super-cycle. Determine 4 is a graph of the magnitudes of the bottom 32 harmonics of an n = 4, b = 8 super-cycle PWM. The graph offers proof of the advantage of this strategy.
Determine 4 First 32 harmonics of an n=4, b=8 super-cycle PWM. Spectra are displayed for X=1 by 8. (Spectra of X=9 by 15 are the identical as these proven.)
The X-sequence’s vitality is comparatively low, having solely 0 by 2n-1 one-states, nevertheless it additionally presents the bottom frequency element, fclk/2n+b Hz. The S-sequence usually accommodates essentially the most vitality by far (aside from cases of very small responsibility cycles), however its smallest frequency element is noticeably increased at Fclk/2b Hz. Among the many X sequences, X = 1 offers the most important amplitude for its first harmonic: 2-11 at fclk/2n+b Hz. The S sequence’s spectrum begins on the X sequence’s harmonic quantity 24 = 16 and produces its largest amplitude of two/π for that harmonic when S = 211. If this had been a regular PWM (an n = 0 super-cycle—no super-cycle in any respect that’s, only a regular PWM), then that amplitude of two/π would seem at frequency which is 16 occasions decrease. The usual PWM presents a way more extreme filtering drawback. Its filter would take so much longer to settle in response to an obligation cycle change due to the a lot bigger quantity of low frequency attenuation required.
Evaluating the filters for (n+b)-bit commonplace and super-cycle PWMs
The filtered AC regular state time-domain contributions of each the usual and the super-cycle (with its X and S sequences) PWMs needs to be lower than some fraction α of the voltage of the PWMs’ one-state. An affordable worth of α is 2-(n+b+1), ½ LSB. This interprets to an attenuation issue of 1/4 on the first harmonic of the X sequence. It’s lucky that even a easy two-component R-C filter assembly this requirement will sufficiently attenuate all increased X sequence harmonics, so there are not any extra constraints to fulfill to suppress them. The 16th X harmonic frequency is that of the primary S harmonic. Its PWM vitality requires an attenuation issue of (π/2)·2-(n+b+1) at a 50% responsibility cycle. Once more, any low move filter assembly this requirement will adequately attenuate the remaining S-sequence harmonics. For an Fclk = 20 MHz, Determine 5 and Determine 6are graphs of the frequency and time area step responses of threerd order filters (two op-amps, 3 resistors, and three capacitors) assembly these necessities for normal 12-bit and super-cycle n = 4, b = 8 (12-bit) PWMs.
Determine 5 The frequency responses of filters for normal and super-cycle n = 4 bit PWMs with 12 bits of decision. The maxima of the peaked waveforms are the utmost responses allowed for the filters on the peaked frequencies. The filters be sure that the regular state time area vitality at their outputs is lower than ½ LSB of Full Scale.
Determine 6 The log of absolutely the worth of time responses of filters for normal and super-cycle n = 4 bit PWMs with 12 bits of decision. The a lot shorter settling time of the super-cycle PWM is clearly evident.
Easing low move analog filter necessities
When partnered with an applicable analog filter, an strategy to PWM embodiment out there in {hardware} in an present microprocessor [1] affords considerably shorter settling occasions than does a regular PWM. This strategy may be carried out with the help of a small quantity of software program in virtually any microcontroller.
Christopher Paul has labored in numerous engineering positions within the communications business for over 40 years.
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